<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[RSS Feed]]></title><description><![CDATA[RSS Feed]]></description><link>http://direct.ecency.com</link><image><url>http://direct.ecency.com/logo512.png</url><title>RSS Feed</title><link>http://direct.ecency.com</link></image><generator>RSS for Node</generator><lastBuildDate>Sun, 12 Apr 2026 22:29:05 GMT</lastBuildDate><atom:link href="http://direct.ecency.com/created/clocking/rss.xml" rel="self" type="application/rss+xml"/><item><title><![CDATA[Pickle of Carandas- plum,😋 Bengal-currants, Black currants]]></title><description><![CDATA[Greetings from Dhaka Bangladesh. Today I am going to talk about preparing pickle of carandas- plum fruit. Today, I have no class in the morning. I have class in the afternoon. So I am free in the morning.]]></description><link>http://direct.ecency.com/hive-120586/@arahman/pickle-of-carandas-plum-bengal-currants-black-currants</link><guid isPermaLink="true">http://direct.ecency.com/hive-120586/@arahman/pickle-of-carandas-plum-bengal-currants-black-currants</guid><category><![CDATA[hive-120586]]></category><dc:creator><![CDATA[arahman]]></dc:creator><pubDate>Wed, 26 Jun 2024 04:03:09 GMT</pubDate><enclosure url="https://images.ecency.com/p/JvFFVmatwWHT5Fvr9KYC2gxEN3P7oD11Skv4rcAkffgGn4t6x3aMs7FLQjb6k9kjdUreAw11bqsxBFUDugFMbcaXzBrRniss7q5tnyRAFwhXrQCFVNpemwb1R7PSSpz1BN2pnkHeai?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Interfaces in SystemVerilog (part 2)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to continue with Interfaces. This is part 2 and so I highly suggest]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-interfaces-in-systemverilog-part-2</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-interfaces-in-systemverilog-part-2</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Thu, 23 Dec 2021 14:53:54 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Ugandan knuckles *clocking*]]></title><link>http://direct.ecency.com/meme/@thajokkeftw/ugandan-knuckles-clocking</link><guid isPermaLink="true">http://direct.ecency.com/meme/@thajokkeftw/ugandan-knuckles-clocking</guid><category><![CDATA[meme]]></category><dc:creator><![CDATA[thajokkeftw]]></dc:creator><pubDate>Thu, 11 Jan 2018 13:10:12 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk7EHeT1aYjzebg2hC7hkthT45eJKptHUSHBCDn5EVrTAJNXjwUcVj6LMn2uL?format=match&amp;mode=fit" length="0" type="false"/></item></channel></rss>