<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[RSS Feed]]></title><description><![CDATA[RSS Feed]]></description><link>http://direct.ecency.com</link><image><url>http://direct.ecency.com/logo512.png</url><title>RSS Feed</title><link>http://direct.ecency.com</link></image><generator>RSS for Node</generator><lastBuildDate>Mon, 13 Apr 2026 03:35:34 GMT</lastBuildDate><atom:link href="http://direct.ecency.com/created/combinational/rss.xml" rel="self" type="application/rss+xml"/><item><title><![CDATA[Logic Design - Circuit Examples in SystemVerilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to get into Circuit Examples. Both combinational and sequential logic]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-circuit-examples-in-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-circuit-examples-in-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 16 Feb 2022 10:10:33 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Combinational Logic Examples [Verilog]]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into Combinational Logic Examples, as promised in the previous part. The first]]></description><link>http://direct.ecency.com/hive-169321/@drifter1/logic-design-combinational-logic-examples-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-169321/@drifter1/logic-design-combinational-logic-examples-verilog</guid><category><![CDATA[hive-169321]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 13 Jul 2021 15:20:24 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Combinational Logic in Verilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on the Hardware Description Language (HDL) Verilog to cover how Combinational Logic is defined]]></description><link>http://direct.ecency.com/hive-169321/@drifter1/logic-design-combinational-logic-in-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-169321/@drifter1/logic-design-combinational-logic-in-verilog</guid><category><![CDATA[hive-169321]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 05 Jul 2021 16:51:09 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item></channel></rss>