<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[RSS Feed]]></title><description><![CDATA[RSS Feed]]></description><link>http://direct.ecency.com</link><image><url>http://direct.ecency.com/logo512.png</url><title>RSS Feed</title><link>http://direct.ecency.com</link></image><generator>RSS for Node</generator><lastBuildDate>Wed, 22 Apr 2026 00:04:09 GMT</lastBuildDate><atom:link href="http://direct.ecency.com/created/fpga/rss.xml" rel="self" type="application/rss+xml"/><item><title><![CDATA[My Report about PIC16F84A Microcontroller Implementation on Verilog Hardware Description Language]]></title><description><![CDATA[Note This is one of my Doctoral assignment from Advanced Computer Architecture II Course which has never been published anywhere and I, as the author and copyright holder, license this assignment customized]]></description><link>http://direct.ecency.com/engineering/@fajar.purnama/my-report-about-pic16f84a-microcontroller-implementation-on-verilog-hardware-description-language</link><guid isPermaLink="true">http://direct.ecency.com/engineering/@fajar.purnama/my-report-about-pic16f84a-microcontroller-implementation-on-verilog-hardware-description-language</guid><category><![CDATA[engineering]]></category><dc:creator><![CDATA[fajar.purnama]]></dc:creator><pubDate>Mon, 22 Mar 2021 22:51:27 GMT</pubDate><enclosure url="https://images.ecency.com/p/7b4bio5hobgskW8qdPdvSqcwwJTvbiCMpGmRey1Rtd8H5rRxMKzoQ8McboCy4hiV4gYqabfkKVcdMCUwsMZTfWqhXzwT2r7YNcswqHEjQk7SmCHVbfHtVkPbgTVTrGjrqLhy4dHps8V5GvzEGzkcAmqxWarr?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Glasgow Interface Explorer is an iCE40 FPGA based hardware debugging tool (crowdfunding)]]></title><description><![CDATA[We've seen some pretty interesting boards for hardware hackers and reverse engineers in recent months with the likes of Ollie and Tigard USB debug boards that allow interfacing various hardware interfaces]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/glasgowinterfaceexplorerisanice40fpgabasedhardwaredebuggingtoolcrowdfunding-dzumhe66opi31i8ogzub</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/glasgowinterfaceexplorerisanice40fpgabasedhardwaredebuggingtoolcrowdfunding-dzumhe66opi31i8ogzub</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Wed, 23 Dec 2020 16:05:00 GMT</pubDate><enclosure url="https://images.ecency.com/p/3W72119s5BjWWp7op8RxWdkjy4kUCemTAwmVkXQNoMJGjGyAuc9U4AWBJZ95sDjHd64VsgAL6pzZMExGEdXrrfmrWXRjtNUFdxQpdFvfZgeeXG9CyRw2og?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Acorn 215 - Xilinx Artix-7 200T FPGA with 1Gb DRAM - $US70 (with payment in crypto)]]></title><description><![CDATA[The Acorn 215 (aka Nitefury) gives you access to a development or accelerator FPGA board with the Xilinx Artix 7-200T FPGA, 1Gb of DDR3 DRAM, PCIE Gen2 x 4. It also has 4 LDVS pairs + 4 GPIO or 12 or GPIO]]></description><link>http://direct.ecency.com/fpga/@apshamilton/acorn-215-xilinx-artix-7-200t-fpga-with-1gb-dram-usdus70-with-payment-in-crypto</link><guid isPermaLink="true">http://direct.ecency.com/fpga/@apshamilton/acorn-215-xilinx-artix-7-200t-fpga-with-1gb-dram-usdus70-with-payment-in-crypto</guid><category><![CDATA[fpga]]></category><dc:creator><![CDATA[apshamilton]]></dc:creator><pubDate>Sun, 08 Nov 2020 10:38:33 GMT</pubDate><enclosure url="https://images.ecency.com/p/5s4dzRwnVbzGj7bKbpX3Re3oksLn2ZQ6pnAaMBYVUd1Q75xWRqFivYMAawuTVT79q69UY4wnkYrcwoCrUwZ8acWHYS56ATqZ8vPnsPwiC4iKV3PFmPDkcF8rnK9oQPsXZHAgxqQMqEmbzZdQcC4QS6BjEYi8DXhUSfeMvP8?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Simple FPGA Design using Xilinx ISE 14.7]]></title><description><![CDATA[IntroductionHello it's a me again drifter1! After covering FPGA Design using Altera/Intel 's Quartus a few years ago on Steemit, its finally time to get into Xilinx FPGAs as well. I currently own a Spartan-6]]></description><link>http://direct.ecency.com/hive-196387/@drifter1/logic-design-simple-fpga-design-using-xilinx-ise-14-7</link><guid isPermaLink="true">http://direct.ecency.com/hive-196387/@drifter1/logic-design-simple-fpga-design-using-xilinx-ise-14-7</guid><category><![CDATA[hive-196387]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 03 Nov 2020 17:40:54 GMT</pubDate><enclosure url="https://images.ecency.com/p/4qEixipsxSf1NbVHAm7jDh3an7o63gpPHJtqvFYK7FD25sate1R4pV1TE6x4Uu9HoU?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[How to start mining Cortex (CTXC)? Pool Mining]]></title><description><![CDATA[#Cortex is a decentralized AI autonomous system. The blockchain wants to make #AI consensus available for contracts. Traditional EVM is not able to run a smart contract on full node with complex inference]]></description><link>http://direct.ecency.com/cortex/@herominers/how-to-start-mining-cortex-ctxc-pool-mining</link><guid isPermaLink="true">http://direct.ecency.com/cortex/@herominers/how-to-start-mining-cortex-ctxc-pool-mining</guid><category><![CDATA[cortex]]></category><dc:creator><![CDATA[herominers]]></dc:creator><pubDate>Sun, 04 Oct 2020 09:28:21 GMT</pubDate><enclosure url="https://images.ecency.com/p/2Qhhdda6QnbewmLm8NhwoBxEay1M6U4AZ7zB9Sh5xfB1877F4nYmkathTEouhLyh955fr3WnWTB5jzmMFhaW?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[How to mine Cortex (CTXC)? Pool Mining]]></title><description><![CDATA[#Cortex is a decentralized AI autonomous system. The blockchain wants to make #AI consensus available for contracts. Traditional EVM is not able to run a smart contract on full node with complex inference]]></description><link>http://direct.ecency.com/cortex/@herominers/how-to-mine-cortex-ctxc-pool-mining</link><guid isPermaLink="true">http://direct.ecency.com/cortex/@herominers/how-to-mine-cortex-ctxc-pool-mining</guid><category><![CDATA[cortex]]></category><dc:creator><![CDATA[herominers]]></dc:creator><pubDate>Sat, 03 Oct 2020 22:29:48 GMT</pubDate><enclosure url="https://images.ecency.com/p/2Qhhdda6QnbewmLm8NhwoBxEay1M6U4AZ7zB9Sh5xfB1877F4nYmkathTEouhLyh955fr3WnWTB5jzmMFhaW?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Have you met MiSTer? Is FPGA the future of Retro Gaming?]]></title><description><![CDATA[For many, MiSTer, and FPGA projects like it, are the future of retro computing and gaming. Why? What about it has people so excited that they will pay 4x the price or more? How would you like a compact]]></description><link>http://direct.ecency.com/technology/@makerhacks/mister-fpga-retrogaming</link><guid isPermaLink="true">http://direct.ecency.com/technology/@makerhacks/mister-fpga-retrogaming</guid><category><![CDATA[technology]]></category><dc:creator><![CDATA[makerhacks]]></dc:creator><pubDate>Tue, 11 Aug 2020 17:57:57 GMT</pubDate><enclosure url="https://images.ecency.com/p/23KQwnti57stuXpnvnU2ByoTTe7rtyo8v5uYk1kPymfyjguJmftL7537rc6zaBjCJiDXLrSBLGCNRGaaZQGBQoS8FCNvtHc?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[zGlue Launches the Open Chiplet Initiative in Collaboration with  Google and Antmicro]]></title><description><![CDATA[We first covered zGlue's ZiP (zGlue Integration Platform) in 2018 as the company introduced its multi-chip module similar to SiP (system-in-package) via a crowdfunding campaign. Just like SiP, the technology]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/zgluelaunchestheopenchipletinitiativeincollaborationwithgoogleandantmicro-6qrjv9895y</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/zgluelaunchestheopenchipletinitiativeincollaborationwithgoogleandantmicro-6qrjv9895y</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Mon, 22 Jun 2020 16:00:00 GMT</pubDate><enclosure url="https://images.ecency.com/p/2gsjgna1uruvZzmfd7k2Jr9EktquLgfDD6gpgPPZfRPpJo6u31Y1WHyoCMEju4QjanfdcgMbbWSPyVgX8wsdrWVCBnNKzTxkv1HjatdDNWXMswmYei?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Efinix Releases Three RISC-V Software-Defined SoC's Optimized for Trion FPGA's]]></title><description><![CDATA[Efinix has announced three RISC-V Software-defined SoC's based on Charles Papon's VexRiscv core and optimized for the company's Trion T8 to T120 FPGA's. VexRiscv is a 32-bit RISC-V CPU usingÂ  RISCV32I]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/efinixreleasesthreerisc-vsoftware-definedsocsoptimizedfortrionfpgas-hw4f8h6z2e</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/efinixreleasesthreerisc-vsoftware-definedsocsoptimizedfortrionfpgas-hw4f8h6z2e</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Sat, 06 Jun 2020 16:45:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/8SzwQc8j2KJbSdz9UQktmmuMijpr1t3etQ6mSqpbAafhoYV2fsMsEHwgu6KeLn3kx8ZWcUhuhJw6QFc5ySsz2oKu9kWjd7qWJam1K3HUtK1YwxAQp6a?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[FPGA Wizards - It Can Run DOOM]]></title><description><![CDATA[Cool projects emerge all the time and I love the nostalgic ones that bring my favourite games or pieces of software forward in time. The arrival of Central Processing Units (CPUs) was a ground breaking]]></description><link>http://direct.ecency.com/fpga/@lockhart/fpga-wizards-it-can-run-doom</link><guid isPermaLink="true">http://direct.ecency.com/fpga/@lockhart/fpga-wizards-it-can-run-doom</guid><category><![CDATA[fpga]]></category><dc:creator><![CDATA[lockhart]]></dc:creator><pubDate>Thu, 14 May 2020 00:49:18 GMT</pubDate><enclosure url="https://images.ecency.com/p/4W3i2hyrJTVfeKM2MDXc1GvPw8wHjk15kZHuBFTiPczob7kvaCE?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Bloguer: deux ans plus tard]]></title><description><![CDATA[Salut tout le monde. Ici Klebs et aujourd'hui, je vais revenir sur mon parcours jusqu'à présent. Comment suis-je passé d'un blog sur les jeux vidéo rétros à un blog sur les jeux vidéo sur Linux? Pourquoi]]></description><link>http://direct.ecency.com/steempress/@lesateliersphv/bloguerdeuxansplustard-mxo4oao33l</link><guid isPermaLink="true">http://direct.ecency.com/steempress/@lesateliersphv/bloguerdeuxansplustard-mxo4oao33l</guid><category><![CDATA[steempress]]></category><dc:creator><![CDATA[lesateliersphv]]></dc:creator><pubDate>Wed, 15 Apr 2020 06:33:06 GMT</pubDate><enclosure url="https://images.ecency.com/p/Zskj9C56UonaJS8gwPheofokR2Gvko3GAFu2bdu91m9anpbSrjVt4hsvPSi8pumt5rMWx9B3qmqSUBt5ikZgsBWUeDyk3LmT6Bys5spZogoddZ8dJZGz?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[ESP Open Source Research Platform Enables the Development of RISC-V & Sparc SoC's with Accelerators]]></title><description><![CDATA[FOSDEM 2020 will take place next week, and there will be several interesting talks about open-source hardware and software development. One of those is entitled "Open ESP â�� The Heterogeneous Open-Source]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/espopensourceresearchplatformenablesthedevelopmentofrisc-vsparcsocswithaccelerators-ahcqr4agw2</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/espopensourceresearchplatformenablesthedevelopmentofrisc-vsparcsocswithaccelerators-ahcqr4agw2</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Sun, 26 Jan 2020 21:50:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/Zskj9C56Uonf2AFEPyrjWdC6TE2BLtJiDrxTB4V3oHbq6RxiNZH6hfnP6vVHpHqAzLNVhbHZav5LMw4KSWVspJwrC8tKPywksuihXzo8Y5CbKtuy8FtA?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Lattice Introduces CrossLink-NX FPGA for Edge AI & Embedded Vision]]></title><description><![CDATA[Lattice CrossLink-NX FPGA Lattice Semiconductor has announced the first product associated with its Nexus Platform, the CrossLink-NX FPGA designed for embedded vision and Edge AI applications. There are]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/latticeintroducescrosslink-nxfpgaforedgeaiembeddedvision-nr6yyun3et</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/latticeintroducescrosslink-nxfpgaforedgeaiembeddedvision-nr6yyun3et</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Thu, 09 Jan 2020 14:50:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/EfcLDDAkyqguXw9VbV7HW8gabvPSrfEHLFktYten5TKHpUfGTyGQxQPvifNN1bhzHyCyfWHpfc5shJ8pqnXAdxTbYARGA?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[OpenWiFi Open-Source Linux-compatible WiFi Stack Runs on FPGA Hardware]]></title><description><![CDATA[WiFi is omnipresent on most connected hardware, and when it works it's great, but when there are issues oftentimes they can not be solved because the firmware is a closed-source binary. I understand companies]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/openwifiisanopen-sourcelinuxwifistackrunningonfpgahardware-5f0m05z5gk</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/openwifiisanopen-sourcelinuxwifistackrunningonfpgahardware-5f0m05z5gk</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Mon, 16 Dec 2019 16:50:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/EfcLDDAkyqguXw9VbV7HW8gabvPSrfEHLFktYten5TKHpUfGTyGQxQPvifNN1bhzHyCyfTyCWXnwngfRFk7Gu72GgMzYn?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[How To Mine Nervos CKB | No More GPU Mining - FPGA Mining Tutorial & Staking]]></title><description><![CDATA[The ultimate guide on how to mine Nervos CKB is here! Nervos CKB was originally GPU mined but now FPGA mining is the most profitable and efficient for CKB. Here's the best mining tutorial for Nervos CKB]]></description><link>http://direct.ecency.com/mining/@voskcoin/how-to-mine-nervos-ckb-or-no-more-gpu-mining-fpga-mining-tutorial-and-staking</link><guid isPermaLink="true">http://direct.ecency.com/mining/@voskcoin/how-to-mine-nervos-ckb-or-no-more-gpu-mining-fpga-mining-tutorial-and-staking</guid><category><![CDATA[mining]]></category><dc:creator><![CDATA[voskcoin]]></dc:creator><pubDate>Sat, 14 Dec 2019 00:48:09 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk7EHeT1aYjzebg2hC7hkthT45e4fnnjK3AhAGKTkjBqLXPJi3nqBSfCpkLvr?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[RISC-V based PolarFire SoC FPGA and Devkit Coming in Q3 2020]]></title><description><![CDATA[Microsemi unveiled PolarFire FPGA + RISC-V SoC about one year ago, but at the time, development was done on a $3,000 platform with SiFive U54 powered HiFive Unleashed board combined with an FPGA add-on]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/risc-vbasedpolarfiresocfpgaanddevkitcominginq32020-92jlmf2e56</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/risc-vbasedpolarfiresocfpgaanddevkitcominginq32020-92jlmf2e56</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Thu, 12 Dec 2019 02:10:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/6VvuHGsoU2QDKAf1AQLftrPkzRc9Z5DXXWnCzWGBWixsoC1gAsMuRvpkUmvcTLsewD23uSCxKjguK6wpCBxVJJ7N5HnP3yJ8VU8MProTJep38NReu4AMHJS2maY7e6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Mining Profitability Update on Nervos Testnet Mining Competition | GPU Testnet to FPGA Mainnet?!]]></title><description><![CDATA[We have been GPU and FPGA mining Nervos CKB a recently launched cryptocurrency coin for a couple months now, lets talk about how many coins we mined and how profitable it was! Subscribe to VoskCoin - Graphics]]></description><link>http://direct.ecency.com/mining/@voskcoin/mining-profitability-update-on-nervos-testnet-mining-competition-or-gpu-testnet-to-fpga-mainnet</link><guid isPermaLink="true">http://direct.ecency.com/mining/@voskcoin/mining-profitability-update-on-nervos-testnet-mining-competition-or-gpu-testnet-to-fpga-mainnet</guid><category><![CDATA[mining]]></category><dc:creator><![CDATA[voskcoin]]></dc:creator><pubDate>Fri, 06 Dec 2019 00:56:48 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk7EHeT1aYjzebg2hC7hkthT45dw25YQCrEossEUjTBBPcQTYPrWbNxBRDF3U?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Best Starter FPGA Mining Rig - Hashaltcoin Blackminer F1 Mini + Plus Review | High Profits Low Power]]></title><description><![CDATA[This low cost, low power usage, low heat, low noise, and high profitability FPGA mining rig may be one of the best miner choices in the current cryptocurrency mining landscape. Here's the Hashaltcoin]]></description><link>http://direct.ecency.com/mining/@voskcoin/best-starter-fpga-mining-rig-hashaltcoin-blackminer-f1-mini-plus-review-or-high-profits-low-power</link><guid isPermaLink="true">http://direct.ecency.com/mining/@voskcoin/best-starter-fpga-mining-rig-hashaltcoin-blackminer-f1-mini-plus-review-or-high-profits-low-power</guid><category><![CDATA[mining]]></category><dc:creator><![CDATA[voskcoin]]></dc:creator><pubDate>Wed, 27 Nov 2019 19:48:09 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk7EHeT1aYjzebg2hC7hkthT45eGJPyR9bEMUXpuEysUX2XXBgxXdsLEemK4a?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Earning $15 a day FPGA Mining Nervos CKB | Review & Tutorial on Eaglesong FPGA Miners]]></title><description><![CDATA[New bitstreams or miner programs have been released making FPGA crypto miners super profitable when mining Nervos CKB on Eaglesong. Lets review how to make your FPGA miners more profitable with FPGA mining]]></description><link>http://direct.ecency.com/mining/@voskcoin/earning-usd15-a-day-fpga-mining-nervos-ckb-or-review-and-tutorial-on-eaglesong-fpga-miners</link><guid isPermaLink="true">http://direct.ecency.com/mining/@voskcoin/earning-usd15-a-day-fpga-mining-nervos-ckb-or-review-and-tutorial-on-eaglesong-fpga-miners</guid><category><![CDATA[mining]]></category><dc:creator><![CDATA[voskcoin]]></dc:creator><pubDate>Thu, 21 Nov 2019 22:40:21 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk7EHeT1aYjzebg2hC7hkthT45eMyQpzAmzeUjYKa4QPLdoM1QF47qMw47B1Y?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[GOWIN GW1NRF FPGA Comes with Bluetooth 5.0 LE Radio & 32-bit ARC MCU]]></title><description><![CDATA[I first heard about GOWIN Semiconductor last month when I found out about Sipeed Tang Nano FPGA board going for $5 and featuring GOWIN GW1N FPGA. The company has now announced what it claims is the first]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/gowingw1nrffpgacomeswithbluetooth50leradio32-bitarcmcu-f2o0ldx1pn</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/gowingw1nrffpgacomeswithbluetooth50leradio32-bitarcmcu-f2o0ldx1pn</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Thu, 14 Nov 2019 00:30:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/62PdCouTvNPEAghD4GFuQ8txcW7zuYQRd6yG43v1prtywcc2mV2fZw9vnnKNqC9BPQ7ArstRhzc391PcntkcKmgebyzEj5zZ4RcwoyTagFrsH6e?format=match&amp;mode=fit" length="0" type="false"/></item></channel></rss>