<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[RSS Feed]]></title><description><![CDATA[RSS Feed]]></description><link>http://direct.ecency.com</link><image><url>http://direct.ecency.com/logo512.png</url><title>RSS Feed</title><link>http://direct.ecency.com</link></image><generator>RSS for Node</generator><lastBuildDate>Tue, 21 Apr 2026 10:37:49 GMT</lastBuildDate><atom:link href="http://direct.ecency.com/created/hdl/rss.xml" rel="self" type="application/rss+xml"/><item><title><![CDATA[LDL vs. HDL: The Battle of the Cholesterols Explained]]></title><description><![CDATA[Okay, so cholesterol might sound like the bad guy in your body’s health drama, but it’s actually a VIP player that just needs a little balance. The stars of this show are two types of lipoproteins: LDL]]></description><link>http://direct.ecency.com/hive-193212/@piotrgrafik/ldl-vs-hdl-the-battle-of-the-cholesterols-explained</link><guid isPermaLink="true">http://direct.ecency.com/hive-193212/@piotrgrafik/ldl-vs-hdl-the-battle-of-the-cholesterols-explained</guid><category><![CDATA[hive-193212]]></category><dc:creator><![CDATA[piotrgrafik]]></dc:creator><pubDate>Mon, 06 Jan 2025 08:11:00 GMT</pubDate><enclosure url="https://images.ecency.com/p/8DAuGnTQCLptZgjHUrRAJGcW4y1D4A5QVJJ7zjzqqKdfVHSS6NapSCCAhoYBBm17t3VJLGtQXQhTQ8UCkKJwsLhXS5DunHcN926GkSTHnsjdtmsrkuCL5SwnBkQH2HWss2ZxErQfCpjf3qwwZR4D6o2YSa3L3hU7ryLDnbL3ijY?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - From Verilog To SystemVerilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog with the purpose of extending our knowledge into SystemVerilog. The differences will]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-from-verilog-to-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-from-verilog-to-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Thu, 25 Nov 2021 13:31:30 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Switch Level Modeling [Verilog]]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to cover Switch Level Modeling, which allow us to take the HDL code into the analog]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-switch-level-modeling-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-switch-level-modeling-verilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 16 Nov 2021 16:56:12 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Compiler Directives [Verilog]]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to cover Compiler Directives, some of which have already been covered in previous]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-compiler-directives-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-compiler-directives-verilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 15 Nov 2021 10:57:18 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Module Parameters and Generate Block [Verilog]]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to cover some additional advanced topics. More specifically, we will talk about Module]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-module-parameters-and-generate-block-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-module-parameters-and-generate-block-verilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Thu, 11 Nov 2021 10:58:24 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Functions and Tasks [Verilog]]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to cover some more advanced topics. More specifically, we will talk about Functions]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-functions-and-tasks-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-functions-and-tasks-verilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 09 Nov 2021 16:39:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Sequential Logic Testbench Example [Verilog]]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into a Sequential Logic Testbench Example. So, without further ado, let's get]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-sequential-logic-testbench-example-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-sequential-logic-testbench-example-verilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 03 Nov 2021 12:11:54 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Combinational Logic Testbench Example [Verilog]]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into a Combinational Logic Testbench Example. So, without further ado, let's]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-combinational-logic-testbench-example-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-combinational-logic-testbench-example-verilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Fri, 29 Oct 2021 10:01:00 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Testbenches and Simulation in Verilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into Testbenches and Simulation. So, without further ado, let's get straight]]></description><link>http://direct.ecency.com/hive-169321/@drifter1/logic-design-testbenches-and-simulation-in-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-169321/@drifter1/logic-design-testbenches-and-simulation-in-verilog</guid><category><![CDATA[hive-169321]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 20 Oct 2021 09:06:48 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Finite-State Machine Examples in Verilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into Finite-State Machine Examples. There will be one FSM for each type (Moore,]]></description><link>http://direct.ecency.com/hive-169321/@drifter1/logic-design-finite-state-machine-examples-in-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-169321/@drifter1/logic-design-finite-state-machine-examples-in-verilog</guid><category><![CDATA[hive-169321]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 04 Oct 2021 12:15:48 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Finite-State Machines in Verilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into Finite-State Machines (FSMs). The article will start out with a small]]></description><link>http://direct.ecency.com/hive-169321/@drifter1/logic-design-finite-state-machines-in-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-169321/@drifter1/logic-design-finite-state-machines-in-verilog</guid><category><![CDATA[hive-169321]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 21 Sep 2021 09:35:27 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Sequential Logic Examples in Verilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into Sequential Logic Examples. I was quite busy with the other series, and]]></description><link>http://direct.ecency.com/hive-169321/@drifter1/logic-design-sequential-logic-examples-in-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-169321/@drifter1/logic-design-sequential-logic-examples-in-verilog</guid><category><![CDATA[hive-169321]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 16 Aug 2021 16:47:27 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Sequential Logic in Verilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into how Sequential Logic is defined and implemented. A circuit is considered]]></description><link>http://direct.ecency.com/hive-169321/@drifter1/logic-design-sequential-logic-in-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-169321/@drifter1/logic-design-sequential-logic-in-verilog</guid><category><![CDATA[hive-169321]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 26 Jul 2021 10:15:27 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Combinational Logic Examples [Verilog]]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into Combinational Logic Examples, as promised in the previous part. The first]]></description><link>http://direct.ecency.com/hive-169321/@drifter1/logic-design-combinational-logic-examples-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-169321/@drifter1/logic-design-combinational-logic-examples-verilog</guid><category><![CDATA[hive-169321]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 13 Jul 2021 15:20:24 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Combinational Logic in Verilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on the Hardware Description Language (HDL) Verilog to cover how Combinational Logic is defined]]></description><link>http://direct.ecency.com/hive-169321/@drifter1/logic-design-combinational-logic-in-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-169321/@drifter1/logic-design-combinational-logic-in-verilog</guid><category><![CDATA[hive-169321]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 05 Jul 2021 16:51:09 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Verilog Introduction]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today marks the beginning of a new series on Logic Design where we will be covering the Hardware Description Language (HDL) known as Verilog.]]></description><link>http://direct.ecency.com/hive-169321/@drifter1/logic-design-verilog-introduction</link><guid isPermaLink="true">http://direct.ecency.com/hive-169321/@drifter1/logic-design-verilog-introduction</guid><category><![CDATA[hive-169321]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 29 Jun 2021 13:01:48 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[High Cholesterol (Hypercholesterolemia)]]></title><description><![CDATA[What Is It? Hypercholesterolemia is a condition characterized by very high levels of cholesterol in the blood. Cholesterol is a waxy, fat-like substance that is produced in the body and obtained from foods]]></description><link>http://direct.ecency.com/health/@hafyan/high-cholesterol-hypercholesterolemia</link><guid isPermaLink="true">http://direct.ecency.com/health/@hafyan/high-cholesterol-hypercholesterolemia</guid><category><![CDATA[health]]></category><dc:creator><![CDATA[hafyan]]></dc:creator><pubDate>Sun, 12 Aug 2018 20:52:21 GMT</pubDate><enclosure url="https://images.ecency.com/p/HNWT6DgoBc14riaEeLCzGYopkqYBKxpGKqfNWfgr368M9UMA1Mu5TxMKB5rzTKfgXL1sGVBCXadyqdNKoa12Kqk3EtfpAEq1kgECzPz38mRKQoyKbjXsBpZ4Yer?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Waiting for the hotpot]]></title><description><![CDATA[@haidilao]]></description><link>http://direct.ecency.com/singapore/@lovelydevil/waiting-for-the-hotpot</link><guid isPermaLink="true">http://direct.ecency.com/singapore/@lovelydevil/waiting-for-the-hotpot</guid><category><![CDATA[singapore]]></category><dc:creator><![CDATA[lovelydevil]]></dc:creator><pubDate>Thu, 10 May 2018 12:17:21 GMT</pubDate><enclosure url="https://images.ecency.com/p/W5LtFUPm6g774G2LPx8CTVHrbGQ778Sw45DBMcdD7pN2Y3b9zshzTVVKr5rNs49aujFcY1Y5hfMdjTrxUhSZL88osmA8v1qvD3iQzbzMLAR93RxctpGaakwua1tXLoDwo59F825QqAyXRdSdCvBBXD8AfmgZC?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Alternative ways to reduce cholesterol without drugs]]></title><description><![CDATA[Cholesterol is a wax-like substance this is gift inside the cell membranes of body tissues and is carried inside the blood plasma. it's far a sterol; a combination of alcohol and steroid and is likewise]]></description><link>http://direct.ecency.com/food/@trikpomkposhishi/alternative-ways-to-reduce-cholesterol-without-drugs</link><guid isPermaLink="true">http://direct.ecency.com/food/@trikpomkposhishi/alternative-ways-to-reduce-cholesterol-without-drugs</guid><category><![CDATA[food]]></category><dc:creator><![CDATA[trikpomkposhishi]]></dc:creator><pubDate>Thu, 15 Feb 2018 16:24:48 GMT</pubDate><enclosure url="https://images.ecency.com/p/qjrE4yyfw5pQYiuVvgYiUBP16WHGGN7UNn1BCdGdZRyBCg66niVvdWtBjh2iTtk1H428k34SdgaLi9AJzc2Buy2ZXjjaJiJFAYMbvySvbSycoUubJFYTicAA?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Healthiest Foods on the Planet]]></title><description><![CDATA[Lemons Why They're Healthy: — Just one lemon has more than 100 percent of your daily intake of vitamin C, which may help increase "good" HDL cholesterol levels and strengthen bones. — Citrus]]></description><link>http://direct.ecency.com/lemon/@stepin2017/healthiest-foods-on-the-planet</link><guid isPermaLink="true">http://direct.ecency.com/lemon/@stepin2017/healthiest-foods-on-the-planet</guid><category><![CDATA[lemon]]></category><dc:creator><![CDATA[stepin2017]]></dc:creator><pubDate>Wed, 08 Nov 2017 05:58:18 GMT</pubDate><enclosure url="https://images.ecency.com/p/AmRc67RgYaWVk3GBzTivMGUEW2ebzdB1gE6rbcN3xLHnHenMuozTbPyYyCA2mTK9YK9YVSDHTMwdgdY73gLWkRXZuUsLMySTB8bdTJCzgnqonMNHDKWR1rAtE2gwixjKNvYXK5e5aHnuMy92hwzocBCDTGxweM6N?format=match&amp;mode=fit" length="0" type="false"/></item></channel></rss>