<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[RSS Feed]]></title><description><![CDATA[RSS Feed]]></description><link>http://direct.ecency.com</link><image><url>http://direct.ecency.com/logo512.png</url><title>RSS Feed</title><link>http://direct.ecency.com</link></image><generator>RSS for Node</generator><lastBuildDate>Tue, 28 Apr 2026 02:31:46 GMT</lastBuildDate><atom:link href="http://direct.ecency.com/created/modport/rss.xml" rel="self" type="application/rss+xml"/><item><title><![CDATA[Logic Design - Interfaces in SystemVerilog (part 1)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Interfaces. The topic will be split into two parts! So, without]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-interfaces-in-systemverilog-part-1</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-interfaces-in-systemverilog-part-1</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 22 Dec 2021 10:45:33 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item></channel></rss>