<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[RSS Feed]]></title><description><![CDATA[RSS Feed]]></description><link>http://direct.ecency.com</link><image><url>http://direct.ecency.com/logo512.png</url><title>RSS Feed</title><link>http://direct.ecency.com</link></image><generator>RSS for Node</generator><lastBuildDate>Fri, 17 Apr 2026 23:49:59 GMT</lastBuildDate><atom:link href="http://direct.ecency.com/created/risc-v/rss.xml" rel="self" type="application/rss+xml"/><item><title><![CDATA[Vitalik Buterin Proposed an Architecture Change to Simplify and Speed up Ethereum by up to 100X | EVM Replacement with RISC-V]]></title><description><![CDATA[Pawel Czerwinski | Unsplash Ethereum to this day remains an incredible technology, although there is a discussion addressing the unrealization of its potential. While Bitcoin seems to outperform time and]]></description><link>http://direct.ecency.com/hive-167922/@vikvitnik/vitalik-buterin-proposed-an-architecture-change-to-simplify-and-speed-up-ethereum-by-up-to-100x-evm-replacement-with-riscv-2ak</link><guid isPermaLink="true">http://direct.ecency.com/hive-167922/@vikvitnik/vitalik-buterin-proposed-an-architecture-change-to-simplify-and-speed-up-ethereum-by-up-to-100x-evm-replacement-with-riscv-2ak</guid><category><![CDATA[hive-167922]]></category><dc:creator><![CDATA[vikvitnik]]></dc:creator><pubDate>Mon, 05 May 2025 17:12:27 GMT</pubDate><enclosure url="https://images.ecency.com/p/NTy4GV6ooFRmaCXZ8UYgPhoud1kjiNX8QokLEZtbBKLuLWQ9yt7K3o4XiwVYjjFs2t4X3shxrfwXuFsotEmkqXqBagV42dbEGf3eGQ5cM3XqSQSRXyvxZqgYmduT4hji7Z6KN4LQ8WxZniZ2o8KxQ1MRjTxQSt9QGshxwAFQ?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Ethereum switching to RISC-V?]]></title><description><![CDATA[Ethereum co-founder Vitalik Buterin has proposed a significant change to the network's architecture: replacing the Ethereum Virtual Machine (EVM) with RISC-V, an open-source instruction set architecture.]]></description><link>http://direct.ecency.com/eth/@cryptosimplify/ethereum-switching-to-riscv-fjs</link><guid isPermaLink="true">http://direct.ecency.com/eth/@cryptosimplify/ethereum-switching-to-riscv-fjs</guid><category><![CDATA[eth]]></category><dc:creator><![CDATA[cryptosimplify]]></dc:creator><pubDate>Thu, 24 Apr 2025 10:16:09 GMT</pubDate><enclosure url="https://images.ecency.com/p/3DLAmCsuTe3bf3YoHiUVXbb4vyBgJzWDy5yMWPLBnj4DSsaJDWKypndkMg8QHyAPpx85SmgWp3MsVmWM3hAkLLmED3i3wY9pH61PThnK6HLaqRpFbRwBac9AunaMaVA2AMkLwBpBLvM4cQdz2BPcKkhHjAgRG5L?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Is it worth the RISC-V]]></title><description><![CDATA[Risc-V is currently very bad in performance. Mainly because only the CPU arch is free. this means that any company can print this CPUs, without needing any architecture engineer. But a PC is not just a]]></description><link>http://direct.ecency.com/risc-v/@miningforpennies/is-it-worth-the-risc</link><guid isPermaLink="true">http://direct.ecency.com/risc-v/@miningforpennies/is-it-worth-the-risc</guid><category><![CDATA[risc-v]]></category><dc:creator><![CDATA[miningforpennies]]></dc:creator><pubDate>Sun, 16 Jun 2024 08:45:45 GMT</pubDate></item><item><title><![CDATA[Hyenas and Computer Chips]]></title><description><![CDATA[The above image was made with stable diffusion using the prompt 'hyenas and computer chips.' Today I've been thinking about code. I have a working knowledge of web languages and an intermediate grasp of]]></description><link>http://direct.ecency.com/ai/@mada/hyenas-and-computer-chips</link><guid isPermaLink="true">http://direct.ecency.com/ai/@mada/hyenas-and-computer-chips</guid><category><![CDATA[ai]]></category><dc:creator><![CDATA[mada]]></dc:creator><pubDate>Fri, 21 Apr 2023 00:34:36 GMT</pubDate><enclosure url="https://images.ecency.com/p/21PRtjKRXPQygJ5a3PGGYDUDAUQfmdSVQys4xPJntqrzSecgUXbPqVgcndPZQ3WqDsaGrodsAGFBSTcDkbqE3G3F3rhSepSet14onQst5bUpgRJATYrFFVafeZXbL8phH6M5TiuJfDD1j1JLo2VauCJ?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Armbian 23.02 ARM/RISC-V 操作系统随 Linux 6.1 LTS 内核发布]]></title><description><![CDATA[Armbian 作为基于 Ubuntu 和 Debian 的 Linux 发行版，主要针对 ARM/AArch64 和 RISC-V 空间中的单板计算机进行了优化，并于 2023 年发布了第一个重大更新。Armbian 23.02 作为此 ARM /以 RISC-V 为导向的 Linux 发行版，它是向 Linux 6.1 LTS 内核的迁移，以提供更新的 SoC 和平台支持，以及其他内核改进。 Armbian]]></description><link>http://direct.ecency.com/arm/@ericjiang/armbian2302armrisc-vlinux61lts-s6lqq8byi9d046yiu7rg</link><guid isPermaLink="true">http://direct.ecency.com/arm/@ericjiang/armbian2302armrisc-vlinux61lts-s6lqq8byi9d046yiu7rg</guid><category><![CDATA[arm]]></category><dc:creator><![CDATA[ericjiang]]></dc:creator><pubDate>Tue, 28 Feb 2023 10:33:36 GMT</pubDate><enclosure url="https://images.ecency.com/p/MG5aEqKFcQiBEm1JsYCFfs1abwdgrDNDp77tiaVYyH9fUZebv9aBBrwjxGUQ5V2sFXwwciLAxvEdN3B2Cfja7NiUcxbVhG5eW?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Think Silicon 展示首款 RISC-V 3D GPU]]></title><description><![CDATA[Think Silicon 展示了首款量产 RISC-V 3D GPU 设计。 Think Silicon NEOX G 系列和 A 系列是他们首款基于 RISC-V 的低功耗 GPU 设计。在 Think Silicon宣布嵌入式世界演示 的新闻稿中，他们解释说： NEOX™| G（图形）和 A（深度学习加速器）系列 IP 代表了智能 GPU 架构的新时代，可编程计算着色器在实时操作系统 (RTOS)]]></description><link>http://direct.ecency.com/risc-v/@ericjiang/thinksiliconrisc-v3dgpu-f2xfgtny9dlxyhl7z72f</link><guid isPermaLink="true">http://direct.ecency.com/risc-v/@ericjiang/thinksiliconrisc-v3dgpu-f2xfgtny9dlxyhl7z72f</guid><category><![CDATA[risc-v]]></category><dc:creator><![CDATA[ericjiang]]></dc:creator><pubDate>Tue, 21 Jun 2022 23:09:06 GMT</pubDate><enclosure url="https://images.ecency.com/p/7ohP4GDMGPrVbcMPyAPG638eqdSyzq4Xb9rxr7UewuFkg1MBLg4LmBuJ44ndiikqRtgwHFpHm3ZD7BDs2BftZCBw3ckjjMMY8UvJ?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[XuanTie C906 based Allwinner RISC-V processor to power $12+ Linux SBC's]]></title><description><![CDATA[Alibaba unveiled Xuantie-910 RISC-V core (aka XT910) in 2019 for powerful SoC with up to 16 cores, but an update in 2020 revealed the company planned to have a complete RISC-V core family for a wide range]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/xuantiec906basedallwinnerrisc-vprocessortopower12linuxsbcs-qpjvhgw45wj345rshq9i</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/xuantiec906basedallwinnerrisc-vprocessortopower12linuxsbcs-qpjvhgw45wj345rshq9i</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Mon, 09 Nov 2020 15:20:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/vM1pGHgNcyCmMvkaatN2vcSAHjmp28w9zvtCqam5sSSavdqHDbBFqnx8xJbFwr38vKPnBHZyDF5z2vEq2FAHrajiVQ86Hsi63feBKRFGFJ97yECrFGwuDzBqFZRxzYHT5PHBoRp?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[zGlue Launches the Open Chiplet Initiative in Collaboration with  Google and Antmicro]]></title><description><![CDATA[We first covered zGlue's ZiP (zGlue Integration Platform) in 2018 as the company introduced its multi-chip module similar to SiP (system-in-package) via a crowdfunding campaign. Just like SiP, the technology]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/zgluelaunchestheopenchipletinitiativeincollaborationwithgoogleandantmicro-6qrjv9895y</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/zgluelaunchestheopenchipletinitiativeincollaborationwithgoogleandantmicro-6qrjv9895y</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Mon, 22 Jun 2020 16:00:00 GMT</pubDate><enclosure url="https://images.ecency.com/p/2gsjgna1uruvZzmfd7k2Jr9EktquLgfDD6gpgPPZfRPpJo6u31Y1WHyoCMEju4QjanfdcgMbbWSPyVgX8wsdrWVCBnNKzTxkv1HjatdDNWXMswmYei?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Efinix Releases Three RISC-V Software-Defined SoC's Optimized for Trion FPGA's]]></title><description><![CDATA[Efinix has announced three RISC-V Software-defined SoC's based on Charles Papon's VexRiscv core and optimized for the company's Trion T8 to T120 FPGA's. VexRiscv is a 32-bit RISC-V CPU usingÂ  RISCV32I]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/efinixreleasesthreerisc-vsoftware-definedsocsoptimizedfortrionfpgas-hw4f8h6z2e</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/efinixreleasesthreerisc-vsoftware-definedsocsoptimizedfortrionfpgas-hw4f8h6z2e</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Sat, 06 Jun 2020 16:45:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/8SzwQc8j2KJbSdz9UQktmmuMijpr1t3etQ6mSqpbAafhoYV2fsMsEHwgu6KeLn3kx8ZWcUhuhJw6QFc5ySsz2oKu9kWjd7qWJam1K3HUtK1YwxAQp6a?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[TTGO T-Watch K210 / K210 AIOT Watches Perform Face Detection with Kendryte K210 RISC-V Processor, ESP32 WiSoC]]></title><description><![CDATA[<br TTGO T-Watch K210 AIOT - Click to Enlarge After covering ESP32 based TTGO T-Watch-2020 programmable watch last month, I noticed LilyGO launched "TTGO T-Watch K210 AIOT" watch with Kendryte]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/ttgot-watchk210k210aiotwatchesperformfacedetectionwithkendrytek210risc-vprocessoresp32wisoc-4iif36n2j7</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/ttgot-watchk210k210aiotwatchesperformfacedetectionwithkendrytek210risc-vprocessoresp32wisoc-4iif36n2j7</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Wed, 03 Jun 2020 14:30:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/3HaJVw3AYyXBgjKMvypJPbYu2PXavNNE6z1SdDT44mRHVeEc93QWGYhKbedDsRbHtEU16kD4jMTFK345GtDYnLEnne9tJPDZsFnp38a?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Getting Started with RT-Thread IoT OS Nano RTOS on RISC-V Processors]]></title><description><![CDATA[CNXSoft: This is a guest post by RT-Thread explaining how to create your first program running on their real-time operating system using a GD32VÂ  RISC-V MCU board as an example. This article describes]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/gettingstartedwithrt-threadiotosnanortosonrisc-vprocessors-hbsb2vz4qz</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/gettingstartedwithrt-threadiotosnanortosonrisc-vprocessors-hbsb2vz4qz</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Tue, 25 Feb 2020 19:15:06 GMT</pubDate><enclosure url="https://images.ecency.com/p/62PdCouTvNPEAghD4GFuQ8txcW7zuYQRd6yG43v1prtywcc2mV2fZw9vnnKNqC9BPQ7ArtjvFXoqhhYCbFq7mhcJUgEtuBkjuBwf6kXWf255W4e?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Antmicro GEM ASIC Leverages zGlue Technology to Quickly Bring Custom Arm/RISC-V SoC's to Market]]></title><description><![CDATA[Introduced in 2018, ZiP (zGlue Integration Platform) chip-stacking technology aims to produce chips similar to Systems-in-Package (SiP) but at much lower costs and lead times. We first found it in a Bluetooth]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/antmicrogemasicleverageszgluetechnologytoquicklybringcustomarmrisc-vsocstomarket-r2kij3q1s9</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/antmicrogemasicleverageszgluetechnologytoquicklybringcustomarmrisc-vsocstomarket-r2kij3q1s9</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Tue, 18 Feb 2020 19:30:06 GMT</pubDate><enclosure url="https://images.ecency.com/p/8SzwQc8j2KJbSdz9UQktmmuMijpr1t3etQ6mSqpbAafhoYV2fsMsEHwgu6KeLn3kx8ZWcUhuhJvHuzWhS6k2SGyTCz8xAdrVTzUwaYXUj18z9XN8z8e?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[How to Build & Run Linux on Kendryte K210 RISC-V NOMMU Processor]]></title><description><![CDATA[A few months ago, we wrote that Western Digital was working on Linux & BusyBox RISC-V NOMMU, and managed to boot a minimal Linux OS on Kendryte K210 powered Sipeed Maix Go board. RISC-V NOMMU support]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/howtobuildrunlinuxonkendrytek210risc-vnommuprocessor-3uxh6k0zwg</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/howtobuildrunlinuxonkendrytek210risc-vnommuprocessor-3uxh6k0zwg</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Mon, 17 Feb 2020 19:15:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/Zskj9C56Uonf2AFEPyrjWdC6TE2BLtJiDrxTB4V3oHbq6RxiNZH6hfnP6vVHpHqAzLNVhbHZav6DffE6L2fCfLViLxpVfGqnZRhQ84QSk3GHd3DfkrQv?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[ESP Open Source Research Platform Enables the Development of RISC-V & Sparc SoC's with Accelerators]]></title><description><![CDATA[FOSDEM 2020 will take place next week, and there will be several interesting talks about open-source hardware and software development. One of those is entitled "Open ESP â�� The Heterogeneous Open-Source]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/espopensourceresearchplatformenablesthedevelopmentofrisc-vsparcsocswithaccelerators-ahcqr4agw2</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/espopensourceresearchplatformenablesthedevelopmentofrisc-vsparcsocswithaccelerators-ahcqr4agw2</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Sun, 26 Jan 2020 21:50:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/Zskj9C56Uonf2AFEPyrjWdC6TE2BLtJiDrxTB4V3oHbq6RxiNZH6hfnP6vVHpHqAzLNVhbHZav5LMw4KSWVspJwrC8tKPywksuihXzo8Y5CbKtuy8FtA?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[AndesCore 27-Series Linux RISC-V SoC Features a Vector Processing Unit]]></title><description><![CDATA[AndesCore 27-Series VPU Andes has developed a Linux capable RISC-V based SoC which runs on the first Vector Processing Unit (VPU) that is reported to be groundbreaking in its application ability, especially]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/andescore27-serieslinuxrisc-vsocfeaturesavectorprocessingunit-kimnhn0b3k</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/andescore27-serieslinuxrisc-vsocfeaturesavectorprocessingunit-kimnhn0b3k</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Fri, 13 Dec 2019 14:55:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/USgKoryE83j5SszZjAePSS3vT6tdpU4JJoTNHEVfh5mnWXUVo2TcQcr99wJn9Qd7bw3JNVJwPXfk48iFo3v7G2?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Western Digital Made RISC-V Linux & BusyBox Boot on Sipeed Maix Go Board]]></title><description><![CDATA[The other days we wrote about Getting Started with Embedded Linux on RISC-V in QEMU emulator and noted that currently Linux capable RISC-V hardware is fairly expensive. We also mentioned there was work]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/westerndigitalmaderisc-vlinuxbusyboxbootonsipeedmaixgoboard-gnzefas4d5</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/westerndigitalmaderisc-vlinuxbusyboxbootonsipeedmaixgoboard-gnzefas4d5</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Tue, 03 Dec 2019 19:50:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/qjrE4yyfw5pT5nvNZxWinX2f6LBdx7zRpwL84zLL6XG6FZCG9E7XWmvoiHxHF5Xyvw6oJABvceMDPts9Bc7iAGwFEk1Pi68qtq8E6BNN6zvCRZHhpCePEC1L?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Another GD32 RISC-V Development Kit with LCD By Seeed Studio]]></title><description><![CDATA[Recently we highlighted the $5 Longan Nano, a development kit released by Sipeed for the Gigadevice GD32V RISC-V family of microcontrollers. The Sipeed Longan Nano is powered by the GigaDevice's GD32VF103CBT6,]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/anothergd32risc-vdevelopmentkitwithlcdbyseeedstudio-lr9uc73f9k</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/anothergd32risc-vdevelopmentkitwithlcdbyseeedstudio-lr9uc73f9k</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Mon, 28 Oct 2019 14:10:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/2N61tyyncFaFrUtdm6DsELyQ9bpNXWzAgzR45WY9GXWQ6GmsSsQagbhvYLvLVVahc9RGu3sGvFw4nYT8gyCtiMWmgkZrbQmZ4KCeuVJDLmMHESGTZEvFzAieECP7jmRe1CH5we2r75qQ?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[SiFive U8-Series Out-of-Order RISC-V Core IP Takes on Arm Cortex-A72 Core]]></title><description><![CDATA[Earlier this week, we wrote about SiFive Shield open security platform as the equivalent of Arm TrustZone security technology, but the company had had another important announcement this week with the]]></description><link>http://direct.ecency.com/embedded/@cnxsoft/sifiveu8-seriesout-of-orderrisc-vcoreiptakesonarmcortex-a72core-v4xv1wqkb2</link><guid isPermaLink="true">http://direct.ecency.com/embedded/@cnxsoft/sifiveu8-seriesout-of-orderrisc-vcoreiptakesonarmcortex-a72core-v4xv1wqkb2</guid><category><![CDATA[embedded]]></category><dc:creator><![CDATA[cnxsoft]]></dc:creator><pubDate>Sat, 26 Oct 2019 16:25:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/99pyU5Ga1kwsZcQSWkbR1grcLhUhfbBJGdNTjoJ1EAqxBVp52wYMgC3q6AbNcjHFwYpPJ8dkrpMEgBWMVSrBThVmQZ277zumJTN7UkFVWfmkGiEG3kBND5odu9REBEWkRL?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[EU plans for domestic exascale supercomputer chips based on Risc-V open source ISA]]></title><description><![CDATA[The European Union's consortium to develop European microprocessors for future supercomputers has taken a few more steps towards its goal of delivering a locally made exascale chip by 2025. That is why,]]></description><link>http://direct.ecency.com/risc-v/@iotdevnet/eu-plans-for-domestic-exascale-supercomputer-chips-based-on-risc-v-open-source-isa</link><guid isPermaLink="true">http://direct.ecency.com/risc-v/@iotdevnet/eu-plans-for-domestic-exascale-supercomputer-chips-based-on-risc-v-open-source-isa</guid><category><![CDATA[risc-v]]></category><dc:creator><![CDATA[iotdevnet]]></dc:creator><pubDate>Mon, 23 Jul 2018 14:41:39 GMT</pubDate><enclosure url="https://images.ecency.com/p/2r8F9rTBenJR2FYcqyvEfgLg58CfXxHNai1gevrkubCXoxbEhNmauuWKneK3pcygxBbvSU6mzmnSNCsSzLUmtySddd2UFzz2eHEWxPaXqnkiVKEfFwVsKVkRkWhiJkhMa?format=match&amp;mode=fit" length="0" type="false"/></item></channel></rss>