<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[RSS Feed]]></title><description><![CDATA[RSS Feed]]></description><link>http://direct.ecency.com</link><image><url>http://direct.ecency.com/logo512.png</url><title>RSS Feed</title><link>http://direct.ecency.com</link></image><generator>RSS for Node</generator><lastBuildDate>Mon, 13 Apr 2026 06:44:48 GMT</lastBuildDate><atom:link href="http://direct.ecency.com/created/rtl/rss.xml" rel="self" type="application/rss+xml"/><item><title><![CDATA[Logic Design - Circuit Examples in SystemVerilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to get into Circuit Examples. Both combinational and sequential logic]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-circuit-examples-in-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-circuit-examples-in-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 16 Feb 2022 10:10:33 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Command Line Arguments & Dynamic Casting (SystemVerilog)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Command Line Arguments & Dynamic Casting. These are]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-command-line-arguments-and-dynamic-casting-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-command-line-arguments-and-dynamic-casting-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Thu, 10 Feb 2022 10:35:06 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Assertions in SystemVerilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Assertions. So, without further ado, let's get straight]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-assertions-in-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-assertions-in-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 07 Feb 2022 09:45:54 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Functional Coverage in SystemVerilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Functional Coverage. So, without further ado, let's get]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-functional-coverage-in-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-functional-coverage-in-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Thu, 03 Feb 2022 13:41:15 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Constraint Types in SystemVerilog (part 2)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the various Constraint Types. This is part 2. You can]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-constraint-types-in-systemverilog-part-2</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-constraint-types-in-systemverilog-part-2</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 31 Jan 2022 11:43:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Constraint Types in SystemVerilog (part 1)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the various Constraint Types. The topic will be split]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-constraint-types-in-systemverilog-part-1</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-constraint-types-in-systemverilog-part-1</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Sat, 29 Jan 2022 11:01:24 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Constraint Blocks (SystemVerilog)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Constraint Blocks. Let's note that we will not cover]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-constraint-blocks-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-constraint-blocks-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Thu, 27 Jan 2022 11:03:39 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Constraints and Randomization (SystemVerilog)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Constraints and Randomization. So, without further ado,]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-constraints-and-randomization-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-constraints-and-randomization-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 26 Jan 2022 10:15:09 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Packages in SystemVerilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Packages. So, without further ado, let's get straight]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-packages-in-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-packages-in-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 25 Jan 2022 10:16:42 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Program Blocks in SystemVerilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the Program Block. So, without further ado, let's get]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-program-blocks-in-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-program-blocks-in-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 24 Jan 2022 09:17:18 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Classes in SystemVerilog (part 3)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover more about Classes. This is part 3 and also the final part!]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-classes-in-systemverilog-part-3</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-classes-in-systemverilog-part-3</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Sat, 15 Jan 2022 15:30:33 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Classes in SystemVerilog (part 2)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover more about Classes. This is part 2 and so I highly suggest]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-classes-in-systemverilog-part-2</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-classes-in-systemverilog-part-2</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Thu, 13 Jan 2022 10:07:27 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Classes in SystemVerilog (part 1)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to start getting into Classes. The topic will be split into multiple]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-classes-in-systemverilog-part-1</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-classes-in-systemverilog-part-1</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 11 Jan 2022 10:58:03 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Interfaces in SystemVerilog (part 2)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to continue with Interfaces. This is part 2 and so I highly suggest]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-interfaces-in-systemverilog-part-2</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-interfaces-in-systemverilog-part-2</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Thu, 23 Dec 2021 14:53:54 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Interfaces in SystemVerilog (part 1)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Interfaces. The topic will be split into two parts! So, without]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-interfaces-in-systemverilog-part-1</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-interfaces-in-systemverilog-part-1</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 22 Dec 2021 10:45:33 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Semaphores and Mailboxes (SystemVerilog)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Semaphores and Mailboxes, which are the two other interprocess]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-semaphores-and-mailboxes-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-semaphores-and-mailboxes-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 14 Dec 2021 12:29:27 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Events (SystemVerilog)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Events, which are one of the three main interprocess communication]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-events-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-events-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 13 Dec 2021 12:05:42 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Processes (SystemVerilog)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Processes. So, without further ado, let's dive straight into]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-processes-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-processes-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 07 Dec 2021 09:56:48 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Control Flow (SystemVerilog)]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover some of the additional Control Flow that it provides. Many]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-control-flow-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-control-flow-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Thu, 02 Dec 2021 13:21:24 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - From Verilog To SystemVerilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog with the purpose of extending our knowledge into SystemVerilog. The differences will]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-from-verilog-to-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-from-verilog-to-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Thu, 25 Nov 2021 13:31:30 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item></channel></rss>