<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[RSS Feed]]></title><description><![CDATA[RSS Feed]]></description><link>http://direct.ecency.com</link><image><url>http://direct.ecency.com/logo512.png</url><title>RSS Feed</title><link>http://direct.ecency.com</link></image><generator>RSS for Node</generator><lastBuildDate>Sun, 12 Apr 2026 05:40:39 GMT</lastBuildDate><atom:link href="http://direct.ecency.com/created/testbench/rss.xml" rel="self" type="application/rss+xml"/><item><title><![CDATA[Logic Design - Program Blocks in SystemVerilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the Program Block. So, without further ado, let's get]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-program-blocks-in-systemverilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-program-blocks-in-systemverilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 24 Jan 2022 09:17:18 GMT</pubDate><enclosure url="https://images.ecency.com/p/8hHVpauQQYxe1XPbGxKgUwB6mdDWnBMjMGVBGdxG3cvZBqn7mz3EyZejbre?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Sequential Logic Testbench Example [Verilog]]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into a Sequential Logic Testbench Example. So, without further ado, let's get]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-sequential-logic-testbench-example-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-sequential-logic-testbench-example-verilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 03 Nov 2021 12:11:54 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Combinational Logic Testbench Example [Verilog]]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into a Combinational Logic Testbench Example. So, without further ado, let's]]></description><link>http://direct.ecency.com/hive-163521/@drifter1/logic-design-combinational-logic-testbench-example-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-163521/@drifter1/logic-design-combinational-logic-testbench-example-verilog</guid><category><![CDATA[hive-163521]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Fri, 29 Oct 2021 10:01:00 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Testbenches and Simulation in Verilog]]></title><description><![CDATA[[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on Verilog to get into Testbenches and Simulation. So, without further ado, let's get straight]]></description><link>http://direct.ecency.com/hive-169321/@drifter1/logic-design-testbenches-and-simulation-in-verilog</link><guid isPermaLink="true">http://direct.ecency.com/hive-169321/@drifter1/logic-design-testbenches-and-simulation-in-verilog</guid><category><![CDATA[hive-169321]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 20 Oct 2021 09:06:48 GMT</pubDate><enclosure url="https://images.ecency.com/p/S5Eokt4BcQdk2bA2uG7tg7Gm64PVu8tEgMs8uQPJPfXkTp39wUhCrNu2e2Jy6dW1bCJ6dr6?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - VHDL Testbench and Datatypes]]></title><description><![CDATA[    Drifter Programming here again for another post of VHDL! I had in mind to upload about Testbenches only, but I found out that I never really talked about Datatypes, Objects, Operations]]></description><link>http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-testbench-and-datatypes</link><guid isPermaLink="true">http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-testbench-and-datatypes</guid><category><![CDATA[vhdl]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 27 Sep 2017 14:11:36 GMT</pubDate><enclosure url="https://images.ecency.com/p/368La1qZAv72idE55VWWwjW7nvH42Uk3Q3ux1amgW1UEQGahdjycXguzTbJ25mZg3uLN8YWsJzyj1ZqDk9b3iFrE?format=match&amp;mode=fit" length="0" type="false"/></item></channel></rss>