<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[RSS Feed]]></title><description><![CDATA[RSS Feed]]></description><link>http://direct.ecency.com</link><image><url>http://direct.ecency.com/logo512.png</url><title>RSS Feed</title><link>http://direct.ecency.com</link></image><generator>RSS for Node</generator><lastBuildDate>Sun, 24 May 2026 23:14:28 GMT</lastBuildDate><atom:link href="http://direct.ecency.com/created/vhdl/rss.xml" rel="self" type="application/rss+xml"/><item><title><![CDATA[My Report about PIC16F84A Microcontroller Implementation on Verilog Hardware Description Language]]></title><description><![CDATA[Note This is one of my Doctoral assignment from Advanced Computer Architecture II Course which has never been published anywhere and I, as the author and copyright holder, license this assignment customized]]></description><link>http://direct.ecency.com/engineering/@fajar.purnama/my-report-about-pic16f84a-microcontroller-implementation-on-verilog-hardware-description-language</link><guid isPermaLink="true">http://direct.ecency.com/engineering/@fajar.purnama/my-report-about-pic16f84a-microcontroller-implementation-on-verilog-hardware-description-language</guid><category><![CDATA[engineering]]></category><dc:creator><![CDATA[fajar.purnama]]></dc:creator><pubDate>Mon, 22 Mar 2021 22:51:27 GMT</pubDate><enclosure url="https://i.ecency.com/p/BgxWBRxjvNhnbM9DiyHtCptYaDNF3xx85r8if8spuMjfmb2LoLyt6M42sdCX5N4PAVpKtCUbkYb68zdYDtHqkkJETTxVLn6bWJPo4nWLmKUJ51ygA1K9UCsYSb541GhmYJNQAAJbgzdpC83kjD34qV1FA5496wY1RFzdf3LrcwwDcra?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Implementing modulo2 multiplication of line with matrix in VHDL (part4)]]></title><description><![CDATA[ Custom thumbnail...  Introduction      Hello it's a me Drifter Programming! Today we continue with my small series, where we will be implementing a complete system in]]></description><link>http://direct.ecency.com/programming/@drifter1/logic-design-implementing-modulo2-multiplication-of-line-with-matrix-in-vhdl-part4</link><guid isPermaLink="true">http://direct.ecency.com/programming/@drifter1/logic-design-implementing-modulo2-multiplication-of-line-with-matrix-in-vhdl-part4</guid><category><![CDATA[programming]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Thu, 28 Jun 2018 18:07:12 GMT</pubDate><enclosure url="https://i.ecency.com/p/Pufd3b1W2k71Fyj6yAGQvFU1mZgf5VBccyqnLoN9FmjYmLNqrqSviMtr?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Implementing modulo2 multiplication of line with matrix in VHDL (part3)]]></title><description><![CDATA[ Custom thumbnail...    Introduction      Hello it's a me Drifter Programming! Today we continue with my small series, where we will be implementing a complete system]]></description><link>http://direct.ecency.com/programming/@drifter1/logic-design-implementing-modulo2-multiplication-of-line-with-matrix-in-vhdl-part3</link><guid isPermaLink="true">http://direct.ecency.com/programming/@drifter1/logic-design-implementing-modulo2-multiplication-of-line-with-matrix-in-vhdl-part3</guid><category><![CDATA[programming]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 27 Jun 2018 13:31:06 GMT</pubDate><enclosure url="https://i.ecency.com/p/Pufd3b1W2k71Fyj6yAGQvFU1mZgf5VB4JM3qcsoRkKShPPHKagqkHmHg?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Implementing modulo2 multiplication of line with matrix in VHDL (part2)]]></title><description><![CDATA[ Custom thumbnail...    Introduction      Hello it's a me Drifter Programming! After the examinations of the week, me and all my friends where totally exhausted]]></description><link>http://direct.ecency.com/programming/@drifter1/logic-design-implementing-modulo2-multiplication-of-line-with-matrix-in-vhdl-part2</link><guid isPermaLink="true">http://direct.ecency.com/programming/@drifter1/logic-design-implementing-modulo2-multiplication-of-line-with-matrix-in-vhdl-part2</guid><category><![CDATA[programming]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Sun, 24 Jun 2018 10:15:39 GMT</pubDate><enclosure url="https://i.ecency.com/p/Pufd3b1W2k71Fyj6yAGQvFU1mZgf5VNnhV5QAnY7jR2JnLGxbaxrfprJ?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Implementing modulo2 multiplication of line with matrix in VHDL (part1)]]></title><description><![CDATA[Custom thumbnail... Introduction      Hello it's a me Drifter Programming! Today we get back to Logic Design and VHDL to get into the promised "advanced" implementation of a specific]]></description><link>http://direct.ecency.com/programming/@drifter1/logic-design-implementing-modulo2-multiplication-of-line-with-matrix-in-vhdl-part1</link><guid isPermaLink="true">http://direct.ecency.com/programming/@drifter1/logic-design-implementing-modulo2-multiplication-of-line-with-matrix-in-vhdl-part1</guid><category><![CDATA[programming]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Thu, 21 Jun 2018 12:54:54 GMT</pubDate><enclosure url="https://i.ecency.com/p/Pufd3b1W2k71Fyj6yAGQvFU1mZgf5VPWYpcR25iwTQKRcsjyvnx5ZEPx?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - How to write simple ROM in VHDL]]></title><description><![CDATA[Custom thumbnail using: ROM Circuit   Introduction Hello Steemians it's a me Drifter Programming!     Today we get back to Logic Design to talk about the implementation of ROM]]></description><link>http://direct.ecency.com/vhdl/@drifter1/logic-design-how-to-write-simple-rom-in-vhdl</link><guid isPermaLink="true">http://direct.ecency.com/vhdl/@drifter1/logic-design-how-to-write-simple-rom-in-vhdl</guid><category><![CDATA[vhdl]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 05 Jun 2018 20:40:42 GMT</pubDate><enclosure url="https://i.ecency.com/p/CQdwDW6BZfWYLQBqgnkRcz5LPe3JmNeazJDaCoTNa7xePTekSoKbmmtexAC8RLJ?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - How to write simple RAM in VHDL]]></title><description><![CDATA[Custom thumbnail using: RAM Circuit Introduction Hello Steemians it's a me Drifter Programming!    Today we get back to Logic Design to talk about the implementation of many simply types]]></description><link>http://direct.ecency.com/vhdl/@drifter1/logic-design-how-to-write-simple-ram-in-vhdl</link><guid isPermaLink="true">http://direct.ecency.com/vhdl/@drifter1/logic-design-how-to-write-simple-ram-in-vhdl</guid><category><![CDATA[vhdl]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 30 May 2018 08:55:36 GMT</pubDate><enclosure url="https://i.ecency.com/p/CQdwDW6BZfWYLS7GERbwYb7Q5mR4bFzyyU8b888EGh5DBoHDfVqg8L6VmMpY4SA?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA["Enduro" em VHDL]]></title><description><![CDATA[Projeto do 3º trimestre da matéria de Eletrônica Digital. ▶️ DTube ▶️ IPFS]]></description><link>http://direct.ecency.com/vhdl/@isneiqui/s96yzl70</link><guid isPermaLink="true">http://direct.ecency.com/vhdl/@isneiqui/s96yzl70</guid><category><![CDATA[vhdl]]></category><dc:creator><![CDATA[isneiqui]]></dc:creator><pubDate>Sat, 14 Apr 2018 23:49:09 GMT</pubDate><enclosure url="https://i.ecency.com/p/46aP2QbqUqBqwzwxM6L1P6uLNceBDDCM9seTSJP5RrgHYN2WxvSnr9wkrMQwui4bKWy3CEjzRxsj5qnFfe6ck57ZZGEA?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Great VHDL Overview by Altera/Intel !]]></title><link>http://direct.ecency.com/engineering/@ny02rangers/great-vhdl-overview-by-altera-intel</link><guid isPermaLink="true">http://direct.ecency.com/engineering/@ny02rangers/great-vhdl-overview-by-altera-intel</guid><category><![CDATA[engineering]]></category><dc:creator><![CDATA[ny02rangers]]></dc:creator><pubDate>Sun, 28 Jan 2018 14:58:48 GMT</pubDate><enclosure url="https://i.ecency.com/p/S5Eokt4BcQdk7EHeT1aYjzebg2hC7hkthT45eREZa7FEBZrRFYvPzs1syaJiHijBqoc63VG?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - Simple FPGA Design using Quartus in VHDL]]></title><description><![CDATA[    Hello its a me again Drifter Programming! Today we get back to Logic Design to talk about FPGA's and all the basic knowledge you need to get started! I will start off talking about]]></description><link>http://direct.ecency.com/fpga/@drifter1/logic-design-simple-fpga-design-using-quartus-in-vhdl</link><guid isPermaLink="true">http://direct.ecency.com/fpga/@drifter1/logic-design-simple-fpga-design-using-quartus-in-vhdl</guid><category><![CDATA[fpga]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 18 Dec 2017 08:28:18 GMT</pubDate><enclosure url="https://i.ecency.com/p/5CEvyaAfMXebL91AmHNXQJGDUY69XCTUcvYAHTbJat67HyemTjrucboudEzut5WbcUiwphVEoRkuruVEN?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - VHDL Simple ALU Circuit (part 3)]]></title><description><![CDATA[    Hello its me again! Today we will end our Series of creating a Simple ALU Circuit in VHDL with part 3. We will combine all the Components we talked about in part 1 and part 2 in]]></description><link>http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-simple-alu-circuit-part-3</link><guid isPermaLink="true">http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-simple-alu-circuit-part-3</guid><category><![CDATA[vhdl]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 11 Oct 2017 18:17:51 GMT</pubDate><enclosure url="https://i.ecency.com/0x0/https://upload.wikimedia.org/wikipedia/commons/thumb/0/0f/ALU_block.gif/1200px-ALU_block.gif" length="0" type="image/gif"/></item><item><title><![CDATA[Logic Design - VHDL Simple ALU Circuit (part 2)]]></title><description><![CDATA[   Hello it's a me again! Today we continue with part 2 of the VHDL Simple ALU Circuit Series. You can find part 1 here. This time we will get into the Multiplier and Comparator]]></description><link>http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-simple-alu-circuit-part-2</link><guid isPermaLink="true">http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-simple-alu-circuit-part-2</guid><category><![CDATA[vhdl]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Tue, 10 Oct 2017 13:21:54 GMT</pubDate><enclosure url="https://i.ecency.com/0x0/https://upload.wikimedia.org/wikipedia/commons/thumb/0/0f/ALU_block.gif/1200px-ALU_block.gif" length="0" type="image/gif"/></item><item><title><![CDATA[Logic Design - VHDL Simple ALU Circuit (part 1)]]></title><description><![CDATA[    Hello my friends its me Drifter programming! Today we get back to VHDL starting off a small Series. I will start writing Components/Hardware of Computers starting off with an Simple]]></description><link>http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-simple-alu-circuit-part-1</link><guid isPermaLink="true">http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-simple-alu-circuit-part-1</guid><category><![CDATA[vhdl]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Mon, 09 Oct 2017 15:58:12 GMT</pubDate><enclosure url="https://i.ecency.com/p/6VvuHGsoU2QDAnJzwpjeRQtURbFPdHB5UGXHFatpek94f9jh7w7gyNoJWLFbsR1MUQzSTA739ktACFHbQ2r4k6tbjSdPAKva2eZBVSst2fc3fGUVMK3m4bhujMfNgm?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - VHDL Coffee FSM Example]]></title><description><![CDATA[    Hello my friends! Today we get again into VHDL to make a more analytic Example of an FSM. We will implement the FSM and simulate it in Modelsim and also create a Testbench for it]]></description><link>http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-coffee-fsm-example</link><guid isPermaLink="true">http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-coffee-fsm-example</guid><category><![CDATA[vhdl]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Thu, 05 Oct 2017 19:34:33 GMT</pubDate><enclosure url="https://i.ecency.com/p/9vWp6aU4y8kxbgw9LhEFrfEKxyfaYxeA6PcD53UNZayQHjrXrPqcSDqHcyNuiHvofNzkYrzMLqMsC2Ckw1GgRdRhFnS8iQnnMfZeotNq2V4rYihfBMDHfmJQi36vayUvfUv4j4hocZnqHbM5Y?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[VHDL sintetizable IP's for FPGA/ASIC implementation.]]></title><description><![CDATA[Here are a bunch of IP's like UART, SPI, I2C  and other IP's useful to make projects be made faster. I provide the link to the github project until steemit will provide a platform for file storage.]]></description><link>http://direct.ecency.com/programming/@morgothcreator/vhdl-sintetizable-ip-s-for-fpga-asic-implementation</link><guid isPermaLink="true">http://direct.ecency.com/programming/@morgothcreator/vhdl-sintetizable-ip-s-for-fpga-asic-implementation</guid><category><![CDATA[programming]]></category><dc:creator><![CDATA[morgothcreator]]></dc:creator><pubDate>Sat, 30 Sep 2017 08:59:57 GMT</pubDate></item><item><title><![CDATA[VHDL ATMEL Mega/Xmega IP core for FPGA/ASIC implementation.]]></title><description><![CDATA[ I decided to put hardware IP's and C/C++ and other libraries made by me on this platform because remain forever :)  First I will provide a link to the the github project that will  evolve]]></description><link>http://direct.ecency.com/programming/@morgothcreator/vhdl-atmel-mega-xmega-ip-core-for-fpga-asic-implementation</link><guid isPermaLink="true">http://direct.ecency.com/programming/@morgothcreator/vhdl-atmel-mega-xmega-ip-core-for-fpga-asic-implementation</guid><category><![CDATA[programming]]></category><dc:creator><![CDATA[morgothcreator]]></dc:creator><pubDate>Sat, 30 Sep 2017 08:46:39 GMT</pubDate></item><item><title><![CDATA[Logic Design - VHDL Finite-State Machines]]></title><description><![CDATA[   Hi, its me again! Today we will talk about Flying Spaghetti Monsters...just joking. We will talk about Finite-State Machines or FSM's for short! It would be a great idea to check the]]></description><link>http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-finite-state-machines</link><guid isPermaLink="true">http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-finite-state-machines</guid><category><![CDATA[vhdl]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Fri, 29 Sep 2017 08:56:36 GMT</pubDate><enclosure url="https://i.ecency.com/p/JvFFVmatwWHVs8siwdup5w2nxUuY631vYG3YEbsfVQrTZ7akBeDKm7F9hNyod2fgosrgW2g6Q5dyyfV4gzYmAEdjnHwcNT8XV822qCtTD6Tb6mwwBkWFsRzE6D9jz2T6CXByN11V6v?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - VHDL Testbench and Datatypes]]></title><description><![CDATA[    Drifter Programming here again for another post of VHDL! I had in mind to upload about Testbenches only, but I found out that I never really talked about Datatypes, Objects, Operations]]></description><link>http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-testbench-and-datatypes</link><guid isPermaLink="true">http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-testbench-and-datatypes</guid><category><![CDATA[vhdl]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Wed, 27 Sep 2017 14:11:36 GMT</pubDate><enclosure url="https://i.ecency.com/p/368La1qZAv72idE55VWWwjW7nvH42Uk3Q3ux1amgW1UEQGahdjycXguzTbJ25mZg3uLN8YWsJzyj1ZqDk9b3iFrE?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - VHDL Sequential Circuits]]></title><description><![CDATA[    Hey it's me again drifter1! Today we will get into VHDL Sequential Circuit Programming. You can find the Theory here if you want to remember things or just got started! I will today]]></description><link>http://direct.ecency.com/logic/@drifter1/logic-design-vhdl-sequential-circuits</link><guid isPermaLink="true">http://direct.ecency.com/logic/@drifter1/logic-design-vhdl-sequential-circuits</guid><category><![CDATA[logic]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Sun, 24 Sep 2017 17:56:06 GMT</pubDate><enclosure url="https://i.ecency.com/p/7258xSVeJbKnZQ6uFopxQui5pP5BKJLwzQHWAxBVU7UxmiqCaRrFQSv4p6rpBJ6r1bPpE6iQTjy29bExFYtVNgz7YKiTMyooYNaQmX2NN49fqh14vP3bgtoQJmEuftbEG8ZRpsh4ms6QE?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[Logic Design - VHDL Behavioral, Dataflow and Structural Models]]></title><description><![CDATA[    Hello my friends! Today we will get into the differences between the Different Descriptions/Models that we can write a Circuit. I will first explain what Behavioral, Dataflow and]]></description><link>http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-behavioral-dataflow-and-structural-models</link><guid isPermaLink="true">http://direct.ecency.com/vhdl/@drifter1/logic-design-vhdl-behavioral-dataflow-and-structural-models</guid><category><![CDATA[vhdl]]></category><dc:creator><![CDATA[drifter1]]></dc:creator><pubDate>Sat, 23 Sep 2017 15:18:36 GMT</pubDate><enclosure url="https://i.ecency.com/p/8hHVpauQQYxf1UyA6nP3Ei8VNJyR6o2sqbccDudLBpBzPAhHJGEvi91i9U2?format=match&amp;mode=fit" length="0" type="false"/></item></channel></rss>