<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[RSS Feed]]></title><description><![CDATA[RSS Feed]]></description><link>http://direct.ecency.com</link><image><url>http://direct.ecency.com/logo512.png</url><title>RSS Feed</title><link>http://direct.ecency.com</link></image><generator>RSS for Node</generator><lastBuildDate>Mon, 18 May 2026 21:28:31 GMT</lastBuildDate><atom:link href="http://direct.ecency.com/created/vlsi/rss.xml" rel="self" type="application/rss+xml"/><item><title><![CDATA[One Hot Check]]></title><description><![CDATA[We would like to know is only one bit in a vector is set. There are many ways to implement this. Here is one efficient way. We would build a tree of ORs and ANDs. The output valid bit would be set if all]]></description><link>http://direct.ecency.com/blog/@arielpesco/one-hot-check</link><guid isPermaLink="true">http://direct.ecency.com/blog/@arielpesco/one-hot-check</guid><category><![CDATA[blog]]></category><dc:creator><![CDATA[arielpesco]]></dc:creator><pubDate>Tue, 23 Jan 2018 13:39:06 GMT</pubDate></item><item><title><![CDATA[First open-source simulation framework for the assessment of  aging effects in SoC designs]]></title><description><![CDATA[In deeply scaled CMOS technologies, device aging causes transistor performance parameters to degrade over time. While reliable models to accurately assess these degradations are available for devices and]]></description><link>http://direct.ecency.com/utopian-io/@victory622/first-open-source-simulation-framework-for-the-assessment-of-aging-effects-in-soc-designs</link><guid isPermaLink="true">http://direct.ecency.com/utopian-io/@victory622/first-open-source-simulation-framework-for-the-assessment-of-aging-effects-in-soc-designs</guid><category><![CDATA[utopian-io]]></category><dc:creator><![CDATA[victory622]]></dc:creator><pubDate>Mon, 01 Jan 2018 21:50:06 GMT</pubDate><enclosure url="https://i.ecency.com/p/3W72119s5BjWMGm4Xa2MvD5AT2bJsSA8F9WeC71v1s1fKfGkK9mMKuc3LcvF4KigbWg9UsrpEPFzhaNPLGhQTpQpPW4T4qfuzJtmTZAkXA5Vr3xffo5ULD?format=match&amp;mode=fit" length="0" type="false"/></item><item><title><![CDATA[An EDA tool for generating automatically Testbenches used in VLSI System-Level Thermal Simulation]]></title><description><![CDATA[In the electronic design automation field, temperature is a critical property of smart systems, due to its impact on reliability and to its inter-dependence with power consumption. Therefore, the thermal-aware]]></description><link>http://direct.ecency.com/utopian-io/@victory622/an-eda-tool-for-generating-automatically-testbenches-used-in-vlsi-system-level-thermal-simulation</link><guid isPermaLink="true">http://direct.ecency.com/utopian-io/@victory622/an-eda-tool-for-generating-automatically-testbenches-used-in-vlsi-system-level-thermal-simulation</guid><category><![CDATA[utopian-io]]></category><dc:creator><![CDATA[victory622]]></dc:creator><pubDate>Sun, 17 Dec 2017 13:13:57 GMT</pubDate><enclosure url="https://i.ecency.com/p/3W72119s5BjWMGm4Xa2MvD5AT2bJsSA8F9WeC71v1s1fKfGkK9mMKuc3LcvF4KigbWg9UsrpEPFvjcLqJArBAT7c7XCwqMBFAWhy2RX7VXKDJvNQixrrei?format=match&amp;mode=fit" length="0" type="false"/></item></channel></rss>