Abstract
A perfect design for a 6 layer PCB is one characterized by being both immune and quiet. It should be able to control the areas around the loops enabling it to pass the immunity and emission test in the first round. One should be able to pay attention to both components and PCB.
Content
1.Reference Plane
2.The Common 6 Layer PCB Stack-Up Design
3.PCB Plane Cuts Kill EMC
1.Reference Plane
The reference plane is used for transferring return current. In the 4 layer design, layer one has a high-frequency return currency on the second layer and the fourth layer also has a high frequency on the third layer hence there is no difference with the 6 layer PCB.
When the reference planes are moved closer to the routing or signal layers you will have cut up on the loop area that determines the emissions that are radiated and the susceptibility when in high frequency. The following are some of the factors that make the 6 layer stack to work well.
1.The near proximity to the ground by every trace.
2.The near proximity of ground planes and power that creates the planner capacitance.
3.The tracing between the third and first layers which does not require any special treatment.
- The layer 4 reference plane is greater than the distance that between it and layer 2.
2.The Common 6 Layer PCB Stack-Up Design
The best 6 layer PCB design will require a stitching in order to connect two ground planes found in the PCB which in turn are supposed to return the current to the reference planes. There are people who say that adding extra ground planes helps in shielding against emissions and immunity.
3.PCB Plane Cuts Kill EMC
The plane cuts can be devastating to the EMC in both emissions and susceptibility. Plane cuts or voids is when the power or the ground plane has an unintentional or intentional cut through a given portion of a plane. The plane cuts come in different sizes and shapes.
A current return path on the plane is some few thousand inches away and in good designs, the trace runs adjacent to the plane hence making the return current path to be in a close proximity hence making the loop area to be relatively small.
When you introduce some void in the copper plane layer, you will have to create a loop that will be required for trace running across the voids and plane cuts. This makes the current loop area to be much bigger.
Conclusion
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Article Source: https://www.wellpcb.com/6-layer-pcb.html