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latest #verilog created topics on internet
serpent7776
DBuzz
2025-01-14 17:44
Fizzbuzz in #verilog
$ 0.000
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drifter1
STEMGeeks
2022-02-16 10:10
Logic Design - Circuit Examples in SystemVerilog
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to get into Circuit Examples. Both combinational and sequential logic
$ 2.379
64
1
drifter1
STEMGeeks
2022-02-10 10:35
Logic Design - Command Line Arguments & Dynamic Casting (SystemVerilog)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Command Line Arguments & Dynamic Casting. These are
$ 1.239
40
drifter1
STEMGeeks
2022-02-07 09:45
Logic Design - Assertions in SystemVerilog
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Assertions. So, without further ado, let's get straight
$ 11.459
27
darth-azrael
retrocomputing
2026-05-15 17:32
Promoted
Compute! (December 1981)
Compute! was one of the earliest home computer magazines. Early in its history, it focused on 6502 based machines. In 1981 that meant the Commodore CBM/PET, Apple II, Atari and OSI. The December 1981 issue
$ 1.480
149
4
drifter1
STEMGeeks
2022-02-03 13:41
Logic Design - Functional Coverage in SystemVerilog
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Functional Coverage. So, without further ado, let's get
$ 1.569
40
drifter1
STEMGeeks
2022-01-31 11:43
Logic Design - Constraint Types in SystemVerilog (part 2)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the various Constraint Types. This is part 2. You can
$ 0.635
20
drifter1
STEMGeeks
2022-01-29 11:01
Logic Design - Constraint Types in SystemVerilog (part 1)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the various Constraint Types. The topic will be split
$ 0.765
46
drifter1
STEMGeeks
2022-01-27 11:03
Logic Design - Constraint Blocks (SystemVerilog)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Constraint Blocks. Let's note that we will not cover
$ 0.570
37
oadissin
Splinterlands
2026-05-17 19:15
Promoted
Splinterlands Finale: How Season 95 Pushed Me Closer to Champions League /
Happy New Splinterlands season. Past 14 days recap for the past edition showed rapid progress on the ranking point and assets collection. Season 96 Strategy Guide: Stacking SPS, Staking BXC & Fixing
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256
8
drifter1
STEMGeeks
2022-01-26 10:15
Logic Design - Constraints and Randomization (SystemVerilog)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Constraints and Randomization. So, without further ado,
$ 12.194
47
drifter1
STEMGeeks
2022-01-25 10:16
Logic Design - Packages in SystemVerilog
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about Packages. So, without further ado, let's get straight
$ 10.960
41
drifter1
STEMGeeks
2022-01-24 09:17
Logic Design - Program Blocks in SystemVerilog
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to talk about the Program Block. So, without further ado, let's get
$ 10.993
51
drifter1
STEMGeeks
2022-01-15 15:30
Logic Design - Classes in SystemVerilog (part 3)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover more about Classes. This is part 3 and also the final part!
$ 12.690
47
holdeck2
Splinterlands
2026-05-17 22:00
Promoted
From Selling 2-Cent Cards to Building Reserves | My Splinterlands Return
From Selling 2-Cent Cards to Building Reserves | My Splinterlands Return Rebuilding From Ashes
$ 1.045
44
4
drifter1
STEMGeeks
2022-01-13 10:07
Logic Design - Classes in SystemVerilog (part 2)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover more about Classes. This is part 2 and so I highly suggest
$ 0.801
43
drifter1
STEMGeeks
2022-01-11 10:58
Logic Design - Classes in SystemVerilog (part 1)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to start getting into Classes. The topic will be split into multiple
$ 1.154
47
drifter1
STEMGeeks
2021-12-23 14:53
Logic Design - Interfaces in SystemVerilog (part 2)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to continue with Interfaces. This is part 2 and so I highly suggest
$ 2.705
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drifter1
STEMGeeks
2021-12-22 10:45
Logic Design - Interfaces in SystemVerilog (part 1)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Interfaces. The topic will be split into two parts! So, without
$ 13.466
321
1
igormuba
GEMS
2026-05-15 15:18
Promoted
You Can Code 8x Faster With AI, But You Cannot Review 8x Faster
AI write sa lot very fast and the code works but it AI doesn't know the full codebase. If an AI writes code from scratch the more it writes the worse it gets, if a human writes code from scratch the more
$ 2.149
113
3
drifter1
STEMGeeks
2021-12-14 12:29
Logic Design - Semaphores and Mailboxes (SystemVerilog)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Semaphores and Mailboxes, which are the two other interprocess
$ 16.349
48
1
drifter1
STEMGeeks
2021-12-13 12:05
Logic Design - Events (SystemVerilog)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Events, which are one of the three main interprocess communication
$ 17.498
48
1
drifter1
STEMGeeks
2021-12-07 09:56
Logic Design - Processes (SystemVerilog)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover Processes. So, without further ado, let's dive straight into
$ 2.575
38
drifter1
STEMGeeks
2021-12-02 13:21
Logic Design - Control Flow (SystemVerilog)
[Edit of Image1] Introduction Hey it's a me again @drifter1! Today we continue with the Logic Design series on SystemVerilog in order to cover some of the additional Control Flow that it provides. Many
$ 0.095
24