latest #hdl created topics on internet

Logic Design - From Verilog To SystemVerilog

2021-11-25 13:31

The first part of another series where we will be extending our Verilog knowledge into SystemVerilog

$ 2.250

drifter1

Logic Design - Switch Level Modeling [Verilog]

2021-11-16 16:56

Modeling in the transistor / switch levels using Verilog

$ 0.590

drifter1

Logic Design - Compiler Directives [Verilog]

2021-11-15 10:57

In-depth usage guide on the Compiler Directives of Verilog

$ 13.106

idea-make-rich

Shadow Hunters

2026-03-30 14:48

👉 Guess The Shadow Contest - Round 90

Namaste🙏, Shadow Hunters family! 🎺 Announcement 🎺! Guess The Shadow Contest Round-89 is now closed. Winners will be announced and rewards will be given within the next 24 hours. Guess The Shadow Contest

$ 0.743

drifter1

Logic Design - Module Parameters and Generate Block [Verilog]

2021-11-11 10:58

In-depth guide to Module Parameters and the Generate Block in Verilog HDL

$ 11.968

drifter1

Logic Design - Functions and Tasks [Verilog]

2021-11-09 16:39

In-depth guide on using Functions and Tasks in Verilog

$ 1.520

drifter1

Logic Design - Sequential Logic Testbench Example [Verilog]

2021-11-03 12:11

A simple, full-on example of implementing, simulating and verifying a sequence detector FSM

$ 0.666

drifter1

Logic Design - Combinational Logic Testbench Example [Verilog]

2021-10-29 10:01

A simple, full-on example of implementing, simulating and verifying a half adder circuit

$ 0.966

aljif7

Education

2026-04-04 04:22

A Daily Word in Spanish (#362)

Autopista (la) Blog de @aljif7 PLATAFORMA: Hive FECHA: Viernes 3 de abril de 2026. Área: Educación-Aprendizaje. A Daily Word in Spanish (#362)-Autopista (la) (Sources: Educalingo, a Pictionary, Wikipedia

$ 0.107

drifter1

Logic Design - Testbenches and Simulation in Verilog

2021-10-20 09:06

In-depth guide on testbench design using Verilog

$ 0.238

drifter1

Logic Design - Finite-State Machine Examples in Verilog

2021-10-04 12:15

In-depth examples on FSM modeling using the Verilog HDL

$ 17.934

drifter1

Logic Design - Finite-State Machines in Verilog

2021-09-21 09:35

In-depth guide to modeling any kind of FSM in Verilog using always blocks

$ 6.708

drifter1

Logic Design - Sequential Logic Examples in Verilog

2021-08-16 16:47

Full-on sequential logic implementation examples in Verilog (Flip Flops, Counters and RAM)

$ 7.983

darth-cryptic

genealogy

2026-04-03 21:17

Genealogy: James T Foley (1832-1900)

I am posting some random bits of my genealogy research here with the goal of eventually creating a linked family tree on Hive. Subject: James T Foley (1832-1900)

$ 0.112

drifter1

Logic Design - Sequential Logic in Verilog

2021-07-26 10:15

An article on the various important things to consider when writing sequential logic using Verilog

$ 0.769

drifter1

Logic Design - Combinational Logic Examples [Verilog]

2021-07-13 15:20

Full-on combinational logic implementation examples in the HDL language Verilog

$ 3.909

drifter1

Logic Design - Combinational Logic in Verilog

2021-07-05 16:51

An article on the various ways of modeling and writing combinational logic using Verilog

$ 0.264

drifter1

Logic Design - Verilog Introduction

2021-06-29 13:01

I'm back guys! This is the first part of my new series on the HDL language Verilog, which is used for hw design and dev.

$ 24.352

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ai-seedfinder

bitcoin

2026-02-17 15:59